physical layer product VSC7321 features: t en triple-speed ethernet macs w/support for rgmii/gmii/mii i ntegrated gbe serdes for direct connection to optical modules intelligent vlan and mpls identification loss less flow control in metro applications up to 10km 10gbe mac w/integrated xaui serdes interface compliant to ieee 802.3ae low pin count, low power oif spi-4.2 system interface e xtensive loopback capabilities for both line and system side configurable parallel or serial cpu interface dual miim interface for managing phy devices independent egress and ingress shaping/policing rate limiting in 1 mb/s increments 802.3ad compliant link aggregation and trunking statistical support for rmon 1 (rfc2819), ieee 802.3 annex 30a, and snmp (rfc 1213, 1573, and 1643) s upports both minimum size 64b frames as well as 9600b jumbo frames au tomatic generation of pause frames based on programmable per port fifo watermarks VSC7321 meigs-ii ? - 10 x 1g and 10g ethernet mac chip specifications: implemented in low power 0.18 micron cmos technology, 2.5v/3.3v io industrial temperature range (-40oc to +85oc) standard 5-pin p1149.1 jtag test port packaged in a 728 pin tbga applications: enterprise and metro ethernet switches multi-service provisioning platforms metro sonet/sdh transport (adms) edge and core aggregation routers dwdm transport terminals (wavelength routers) application diagrams: ethernet product pb-VSC7321-002 rgmii/gmii spi-4.2 10 x gbe mac w/ rgmii/gmii VSC7321 npu or asic switch or transceiver backplane or switch interface 10 x gbe mac interfacing to npu or asic phy phy sts-1 grooming tsi packet mapper with vc and gfp 10 x gbe over sonet/sdh using the vsc9118 spi-4.2 backplane interface 10 x gbe mac w/ integrated serdes serial o/e o/e vsc9185 vsc9118 VSC7321 spi-4.2 10 gbe mac w/ integrated xaui xaui backplane or switch interface 10 gbe mac interfacing to npu or asic VSC7321 npu or asic switch or transceiver o/e .com .com .com .com 4 .com u datasheet
for more information on vitesse products visit the vitesse web site at www.vitesse.com or contact vitesse sales at (800) vitesse or sales@vitesse.com vsc7322 ?2002 vitesse semiconductor corporation lansing? is an advanced ethernet mac chip, allowing a system with a standard csix-64 host interface access to 10 tri- speed (10/100/1000 mbit/s) ethernet ports. the 10 separate tri-speed macs support both half-duplex and full duplex at 10/100 mbit/s and full duplex at 1 gbit/s. on-chip fifos capable of handling short-haul flow control are located between the ethernet ports and the csix-64 interface. these fifos are also useful for smoothing bursty traffic on both the csix-64 and the ethernet ports, and for compensating for the bursts generated when aggregating links. lansing? can be used together with meigs-i? in a flexible port aggregation or port trunking mode. the scheme can be based on mac addresses or mpls tags. vsc7322 block diagram: general description: lansing? - 10 x 1 gigabit ethernet mac chip rgmii/rtbi t ri-speed mac 10 x 1gbe fifos statistics csix-64 miim cpu serial i/f these features allow a 10gbe connection to behave like ten separate tri-speed connections, which make integration of 10gbe into existing designs simpler. aggregation can be made between the 10gbe port and csix-64 or directly between the 10gbe port and the 10 tri-speed ports. a dual mii management interface sets up and controls the phys. frames are monitored, and the statistics generated can be analyzed at a later time. all registers can be accessed via the serial or csix-64 interfaces. a comprehensive set of statistics counters supports the rmon 1, ieee802.3, and snmp standards. te st features include cyclic replay of frames at a user definable rate - either built by the external cpu directly inside the fifos or captures from incoming traffic. 741 calle plano camarillo, ca 93012, usa t el: +1 805.388.3700 fax: +1 805.987.5896 www.vitesse.com .com .com .com .com 4 .com u datasheet
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